SYCL Tutorials

The tutorials have now finished but the discussions continue.  We have set-up a dedicated Slack workspace so that authors and attendees can discuss the content of the program.  There are active channels covering the SYCL tutorials as well as the main program (papers, technical presentations and posters) and the Khronos panel discussion.  Registration for the Slack workspace will remain open until May 29th 2020 .

JOIN THE SLACK DISCUSSIONS

An Introduction to SYCL

By Codeplay, Heidelberg University, Intel and Xilinx
Live streamed on Monday 27th April, 2020

SYCL is a programming model that lets developers support a wide variety of devices (CPUs, GPUs, and more) from a single code base. Given the growing heterogeneity of processor roadmaps, moving to a platform-independent model such as SYCL is essential for modern software developers. SYCL has the further advantage of supporting a single-source style of programming from completely standard C++. In this tutorial, we will introduce SYCL and provide programmers with a solid foundation they can build on to gain mastery of this language.

The format will be short video presentations followed by short coding exercises.

Course Outline

  • Introduction to SYCL
  • The basic structure of every SYCL program
  • Device topology and configuring a queue
  • Handling SYCL errors
  • The host-device interface and launching a kernel
  • The fundamental concepts of a SYCL kernel
  • Managing Data in SYCL

Coding Exercises

There will be time allocated for hands on coding exercises during the tutorial and we recommend that you set up your machine or the Intel DevCloud before the tutorial for these exercises. Since there are various implementations of the SYCL standard you have some choices.

We’ll provide instructions during the exercises for all these options.

Use SYCL in the Cloud

The simplest choice is to use DPC++ and the Intel DevCloud because it requires no setup on your machine.
You can access the cloud machine through your web browser or via SSH terminal and run SYCL code on an Intel CPU
Register for access at https://devcloud.intel.com/oneapi/connect/

ComputeCpp

Hardware Supported: Intel CPU/GPU, Arm GPU
Go to https://developer.codeplay.com/products/computecpp/ce/guides for setup instructions

DPC++

Hardware Supported: Intel CPU/GPU/FPGA, NVIDIA GPU
Go to https://software.intel.com/en-us/oneapi/dpc-compiler for setup instructions

hipSYCL

Hardware Supported: AMD GPU, NVIDIA GPU, (Other CPUs where a C++ compiler exists for that CPU that supports OpenMP)
Go to https://github.com/illuhad/hipSYCL for setup instructions

Course Schedule (Pacific Time)

8:0020 minLectureIntroduction to SYCLCodeplay
8:2025 minHands onGetting set upCodeplay
8:4520 minLectureTopology discovery and queue configurationCodeplay
9:0525 minHands onConfiguring a queueCodeplay
9:3020 minLectureDefining kernelsCodeplay
9:5025 minHands onHello worldCodeplay
10:1520 minLectureManaging dataCodeplay
10:3525 minHands onVector addCodeplay
11:001 hourQ&AContinued Discussion and Q&A on chat channelTBD

Full YouTube Live Stream

Individual Sessions

The following individual video presentations were included in the live stream above.

Introduction to SYCL

Topology Discovery and Queue Creation

SYCL Kernel Functions

Managing Data in SYCL

Application Development with SYCL

By Codeplay, Heidelberg University, Intel and Xilinx
Live streamed on Wednesday 29th April, 2020

As a programming model, SYCL is interesting, but its real value comes from its use in writing applications. This second part of the SYCL tutorial covers the ecosystem available to SYCL developers with an insight into some of the features that are being added to the standard, and more details on some of the advanced features. There will also be time during the panel session to pose question to some of the developers involved in defining and implementing the SYCL standard.

The format will be short video presentations followed by live Q&A sessions with experts from Codeplay, Heidelberg University, Intel and Xilinx.

Course Outline

  • Understanding the SYCL implementations
  • Migrating from CUDA to SYCL
  • Unified Shared Memory in SYCL
  • Host Tasks
  • FPGA extensions in SYCL
  • SYCL Implementer Panel and Q&A

Course Schedule (Pacific Time)

8:0040 minLectureOverview of SYCL implementations

  • ComputeCpp
  • DPC++
  • hipSYCL triSYCL
Codeplay, Intel, Heidelberg University, Xilinx
8:4015 minLive Q&A
8:5545 minLectureExpanding the ecosystem

  • DPC++ Compatibility Tool: Migrating from CUDA* to DPC++
  • Offload advisor
  • Nvidia support
Codeplay, Intel
9:4015 minLive Q&A
9:5545 minTBDFuture direction of SYCL

  • Unified Shared Memory
  • Host Task
  • FPGA Extensions
Codeplay, Intel, Xilinx
10:4015 minLive Q&A

Full YouTube Live Stream

Individual Sessions

The following individual video presentations were included in the live stream above.

DPC++ Introduction

An Introduction to hipSYCL

triSYCL

Intel DPC++ Compatibility Tool

Introduction to Offload Advisor

NVidia Support in DCP++

Unified Shared Memory

FPGA Extensions